1. Field of the Invention
The invention relates to a system-in-package, and more particularly, to a system-in-package having a void in the periphery area of a carrier substrate.
2. Description of the Prior Art
The functionality of electronic products continues to increase, and mirror that is the development of packaging processes. Packaging processes continue a trend toward the high density, miniature size, multi-chip, and three dimensional design. In general, various high density package structures commonly utilized today include wafer level packages, three dimensional packages, multi-chip packages, and system-in-package structures. Preferably, an ideal package structure involves the incorporation of virtually all of the integrated circuits into a silicon chip, such as a system on chip (SoC) design. However, how to successfully incorporate the complex circuit functions into a single chip has not only increased the fabrication difficulty, but has also increased the size of the chip and the overall cost and yield of the fabrication process. Hence, a system-in-package structure that emphasizes the traits of small volume, high frequency, high speed, short production cycle, low cost, and the ability to integrate chips with different circuit functions has become a popular packaging technique.
Please refer to FIG. 1. FIG. 1 is a perspective diagram illustrating a system-in-package structure 10 according to the prior art. As shown in FIG. 1, the system-in-package structure 10 includes a carrier substrate 16, in which the surface of the carrier substrate 16 defines a molding area 30 and a periphery area 32. The molding area 30 includes a chip 12 disposed on the carrier substrate 16, an adhesive layer 14 disposed between the carrier substrate 16 and the chip 12, and a molding compound 24 covering the chip 12 and part of the carrier substrate 16. Additionally, the system-in-package structure 10 includes a plurality of wires 18 electrically connected to the chip 12 and the carrier substrate 16 and a plurality of solder balls 22 disposed on the bottom surface of the carrier substrate 16, in which the solder balls 22 are connected to the chip 12 through the circuits (not shown) within the carrier substrate 16. The periphery area 32 includes a solder mask 32 and a plurality of solder pads 36 disposed on the surface of the carrier substrate 16, in which the height of the surface of the solder pads 36 is equivalent to the height of the solder mask 34 surface.
However, the molding compound 24 covering the chip 12 and the carrier substrate 16 often flush out of the molding area 30 and flood the surface of the periphery area 32 during a molding process. Since the height of the solder mask 36 surface is equal to the height of the solder pads 36 surface, excessive molding compound 24 utilized during the molding process will flood. The flood covers the solder pads 36 and the solder mask 34 in the periphery area 32 thereby influencing the ball mounting process thereafter. Consequently, the stability of the passive devices (not shown), active devices (not shown), and solder balls (not shown) disposed on the solder pads 36 is not ideal.